1. Field of the Invention
The present invention relates to a solid-state image sensor comprising a photoelectric transducing portion in which a plurality of photoelectric transducers are provided horizontally in a plurality of rows and vertically in a plurality of columns, respectively.
2. Description of The Prior Art
As a solid-state image sensor, a MOS type solid-state image sensor and a charge coupled device (CCD) type solid-state image sensor are known.
An example of a solid-state image sensor using n-channel MOS transistors (referred to hereinafter as "nMOS transistors") will be described in the following.
FIG. 1 is a plan view showing an example of the structure of a conventional nMOS type solid-state image sensor. This solid-state image sensor comprises: a plurality of nMOS transistors 1 serving as photoelectric transducers provided in a plurality of rows horizontally and in a plurality of columns vertically at distances from each other; a photoelectric transducing portion 2 shown by the dot-and-dash line comprising a plurality of nMOS transistors 1; a horizontal scanning circuit portion 3 provided at a distance from the photoelectric transducing portion 2, in parallel with the horizontal nMOS transistors 1, the horizontal scanning circuit portion 3 including a plurality of commonly connected lines (3a) of the first layer for successively connecting the plurality of nMOS transistors 1 in columns so as to successively scan the lines 3a; and a vertical scanning circuit portion 4 provided at a distance from the photoelectric transducing portion 2, in parallel with the vertical, nMOS transistors 1, the vertical scanning circuit portion 4 including a plurality of commonly connected lines 4a of the second layer for successively connecting the plurality of nMOS transistors 1 in rows so as to successively scan the lines 4a.
FIG. 2 is a sectional view showing partially an array of nMOS transistors in rows in a step where lines of the first layer of a photoelectric transducing portion are formed in a conventional nMOS type solid-state image sensor. In FIG. 2, the same reference characters as in FIG. 1 indicate like parts. The nMOS transistor array in FIG. 2 comprises: an n-type silicon substrate 11; a p-type silicon layer 12 formed on one major surface of the n-type silicon substrate 11 by the epitaxial growth method; a field insulating film 13 formed on one major surface of the p-type silicon layer 12 so as to separate the respective regions assigned for nMOS transistors; p.sup.+ type channel cut regions 14 formed under the field insulating film 13 of the p-type silicon layer 12; nMOS transistors 1 formed by a well known nMOS transistor forming method in the respective nMOS transistor forming regions separated by the field insulating film 13 on the major surface of the p-type silicon layer 12; gate electrodes 15 formed through a gate insulating film 15a in fixed portions in the nMOS transistor forming regions on the major surface of the p-type silicon layer 12; and n-type source regions 16 and n-type drain regions 17 formed by introducing n-type impurity into both outer sides of each gate insulating film 15a of the nMOS transistor forming regions on the major surface of the p-type silicon layer 12. The n-type source regions 16 and the p-type silicon layer 12 in contact therewith constitute photodiodes for photoelectric transducing. The above described nMOS transistor array further comprises an insulating layer film 18 formed over all the upper surfaces of the nMOS transistors 1 and the field insulating film 13, and lines 3a of the first layer formed on the surface of the insulating film layer 18 and connected to the n-type drain regions 17 of the nMOS transistors 1 through openings provided in the insulating film layer 18. A bias power supply 19 for applying bias voltage in a reverse direction is connected between the n-type silicon substrate 11 and the p-type silicon layer 12.
In a conventional example having a structure as described above, when red color light is applied from a direction shown by an arrow L to an n-type source region 16 constituting a photodiode of an nMOS transistor 1, electrons (shown by a reference character E) are generated due to the red color light absorbed in a deep portion of the n-type source region 16 of the nMOS transistor 1. These electrons E flow into an n-type drain region 17 of the above mentioned nMOS transistor 1 through a path shown by an arrow A or flow into an n-type source region 16 of an nMOS transistor 1 adjacent to the above mentioned nMOS transistor 1 through a path shown by an arrow B under the field insulating film 13, irrespectively of turning on or off of the gate electrode 15 of the above mentioned nMOS transistor 1. In order to suppress the flow of electrons E through the path A or B as described above and to prevent the red color sensitivity of a photodiode consisting of an n-type source region 16 from being intensified due to the electrons E so as to relatively increase the blue color sensitivity, bias voltage in a reverse direction is applied between the n-type silicon substrate 11 and the p-type silicon layer 12 by means of the bias power supply 19 so that the electrons E are withdrawn toward the n-type silicon substrate 11. This is particularly effective, as is known, in suppressing occurrence of a color mixture phenomenon, a blooming phenomenon and a smear phenomenon caused by the electrons E flowing through the path A or B when an amount of light larger than the saturation amount is applied to a photodiode consisting of an n-type source region 16.
However, in order to make the electrons E hardly flow through the path A or B, it is necessary to increase the bias voltage in the reverse direction applied between the n-type silicon substrate 11 and the p-type silicon layer 12 and, if the bias voltage is increased, the red color sensitivity of a photodiode consisting of an n-type source region 16 is lowered more than needed. As a result, it is not easy to prevent occurrence of the color mixture phenomenon, the blooming phenomenon and the smear phenomenon.